Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods and structures for using a cover mask for allowing metal lines to be jumped over PC connection features in standard cells, or manufacturing semiconductor devices.
Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another.
In this manner, integrated circuit chips may be fabricated. In some cases, integrated circuit or chips may comprise various devices that work together based upon a hard-coded program. For example, application-specific integrated circuit (ASIC) chips may use a hard-coded program for various operations, e.g., boot up and configuration processes. The program code, in the form of binary data, is hard-coded into the integrated circuit chips.
When designing a layout of various devices with an integrated circuits (e.g., CMOS logic architecture), designers often select pre-designed functional or standard cells comprising various features (e.g., diffusion regions, transistors, metal lines, vias, etc.) and place them strategically to provide an active area of an integrated circuit. One challenge of designing a layout is accommodating ever-increasing density of cell components and still maintain routability for connecting various components of the cells. This is increasingly a challenge as dimensions of these components get smaller, such as for 10 nm or lower integrated circuit designs.
As the dimensions of standard cells become smaller, routing problems tend to increase. Designers have turned to developing technology that include direct connection to a metal layer and middle-of-line (MOL) features, such as CA, CB, and or trench silicide (TS) features, without using intermediate vias. In this technology, routing a metal feature (e.g., M1 feature) may be difficult since it may contact an MOL feature unless the metal features is routed around the MOL feature. This routing around technique can reduce routing efficiency in standard cells.
FIG. 1A illustrates a stylized depiction of a typical standard cell having a metal layer that is in direct connection with an MOL feature. FIG. 1B illustrates a stylized cross-sectional depiction of the cell of FIG. 1A. The cross-sectional view of FIG. 1B is of the view at the dotted line 105 shown in FIG. 1A.
Referring simultaneously to FIGS. 1A and 1B, a cell 100 comprises a plurality of routing tracks (e.g., M1 routing tracks) on which metal routing features may be formed. The cell 100 includes a 1st active area 110 and a 2nd active area 120, in which source/drain features may be formed.
A plurality of PC (gate) features 130 for transistors are formed in the cell 100. A plurality of middle of line (MOL) features may be formed to provide interconnection between source/drain features, as well as for gate features 130. A CA feature 170 may be formed in the cell 100. Further, a CB feature 175 may be formed over a PC feature 130.
FIG. 1B illustrates a cross-sectional view of the cell 100. A substrate layer 150 is formed. A dielectric layer 160, e.g., silicon nitride, is formed above the substrate layer 150. The PC features 130, the CA feature 170, and a CB feature 175 are formed above the substrate layer, within the dielectric layer 160. The 1st metal feature 120a is formed above the dielectric layer 160. The 1st metal feature 120a comes into contact with the CA feature 170 in the region denoted by the circle 140.
The cell 100 is of technology that provides for direct connection from the first metal layer (M1 layer) to MOL features, without using an intermediate via. A plurality of metal features may be also formed in the cell 100. A 1st metal feature 120a and a 2nd metal feature 120b are formed in the cell 100.
The 1st metal feature 120a is formed above the dielectric layer 160. In some cases, the 1st metal feature 120a comes into contact with the CA feature 170 in the region denoted by the circle 140. The coupling of the 2nd metal feature 120b may be desired. However, the coupling of the 1st metal feature 120a to the CA feature 170 (see circle 140) is not desired. In order to avoid this contact (indicated by the circle 140), the 1st metal feature 120a would have to be routed around the CA feature 170. This would require usage of more space, leading to routing and space inefficiencies.
FIG. 2 illustrates a stylized depiction of another example of a typical cell having technology that provides for direct connection from the first metal layer (M1 layer) to MOL features. FIG. 2 illustrates a cell 200 that may be formed using an SADP process. In an SADP process, the metal features that are formed are typically referred to as either “mandrel-metal” features (“MM”) or “non-mandrel-metal” features (“NMM”). As it relates to terminology, the MM features and NMM features are referred to as being different “colors” when it comes to decomposing an overall pattern layout that is intended to be manufactured using an SADP process. Thus, two MM features are said to be of the “same color” and two NMM features are said to be of the “same color,” while an MM feature and an NMM feature are said to be of “different colors.”
The cell 200 comprises metal features of a different colors. A plurality of metal features of a 1st color 220a may be formed, included a 1st power rail 222 coupled to a VDD signal and a 2nd power rail 224 coupled to a VSS signal. The cell 200 may comprise a 1st active area 210a and a 2nd active area 210b. 
A plurality of metal features of a 2nd color 220b may also be formed in the cell 200. The cell 200 also includes a plurality of CA features 270, a plurality of CB features 180, and a plurality of vertical PC (gate) features 220. Some designers have expressed the desire to connect multiple PC features 220 by using a horizontal (wrong way) PC feature 225, as shown in FIG. 2. However, this design would be impractical in state-of-the-art designs, particularly due to the strong dipole illumination required for the modern pitch and gate lengths. Further, using horizontal metal layer features to connect a the PC features 220 may cause inadvertent connections to MOL features, similar to the problems illustrated above with regard to FIG. 1. Routing metal features around MOL features to avoid this issue may cause other problems, such as routing congestion, design error rule violations, etc. Therefore, as described above, there are various inefficiencies, routing difficulties, design rule errors, and other problems associated with the state-of-art.
The present disclosure may address and/or at least reduce one or more of the problems identified above.